1. Field of the Invention
The present invention relates to a method and a device for driving a plasma display panel (PDP).
In an AC type PDP, before addressing for forming a charge distribution in accordance with display data, charge is equalized in all cells. Quality of the equalization affects the success or failure of the addressing. In order to improve quality of a display, it is desired to realize a driving method in which precise equalization can be performed in a short time.
2. Description of the Prior Art
In an AC type PDP, a memory function of a dielectric layer covering display electrodes is utilized. In other words, charge quantity of a cell is controlled in accordance with display data in the addressing, and then a sustaining voltage Vs having alternating polarities is applied to a pair of display electrodes. The sustaining voltage Vs satisfies the following inequality.Vf−Vw<Vs<Vf
Here, Vf denotes a discharge start voltage, and Vw denotes a wall voltage between electrodes.
When the sustaining voltage Vs is applied, a cell voltage (an effective voltage of a voltage applied to the electrode plus the wall voltage) exceeds the discharge start voltage Vf and display discharge is generated only in cells having the wall charge. “Lighting” means to emit light by display discharge. In general, an application period of the sustaining voltage Vs is approximately several microseconds, and the light emission looks continuous. Since the cell of a PDP is a binary light emission element, a half tone is reproduced by setting the number of discharge times in one frame in accordance with a gradation level for each cell. A color display is one type of a gradation display, and a display color is determined by combining luminance levels of three primary colors. The gradation display is realized by making one frame of plural subframes having a luminance weight and by setting the number of total discharge times by combining on and off of lighting for each subframe. In the case of an interlace display, each of plural fields of a frame includes plural subfields, and the lighting control is performed for each subfield. However, contents of the lighting control are the same as that in a progressive display.
Adding to an address period for addressing and a display period (or a sustain period) for generating display discharge plural times in accordance with the luminance weight, a reset period for an initialization is assigned to the subframe so as to equalize charged state of a whole screen before the addressing. At the end of the display period, some cells have relatively much wall charge, and other cells have little wall charge. Therefore, in order to improve reliability of a display, the initialization is performed as an addressing preparation process.
U.S. Pat. No. 5,745,086 discloses an initialization step in which a first and a second ramp voltage are applied to cells sequentially. By applying a ramp voltage having a gentle gradient, light emission quantity in the initialization can be decreased because of characteristics of microdischarge that will be explained below. Thus, drop of contrast is prevented, and the wall voltage can be set to any target value despite of variation of cell structures.
When a ramp voltage having an increasing amplitude is applied to a cell having appropriate quantity of wall charge, microdischarge is generated plural times while the applied voltage increase if the gradient of the ramp voltage is gentle. As the gradient is made further gentle, discharge intensity is decreased and the discharge period is shortened so as to transfer to a continuous discharge form. In the following explanation, periodic discharge and continuous discharge are collectively called “microdischarge”. In the microdischarge, the wall voltage can be set only by a peak voltage value of the ramp waveform. It is because that during the microdischarge even if a cell voltage Vc (=the wall voltage Vw+an applied voltage Vi) applied to a discharge space exceeds a discharge start threshold level (hereinafter, denoted by Vt) as the ramp voltage increases, the cell voltage is always kept at the vicinity of the voltage Vt due to the microdischarge. The microdischarge drops the wall voltage by the same level as the increased level of the ramp voltage. When the final value of the ramp voltage is denoted by Vr and the wall voltage when the ramp voltage reaches the final value Vr is denoted by Vw, the following relationship is satisfied since the cell voltage Vc is maintained at the voltage Vt.Vc=Vr+Vw=VtTherefore, Vw=−(Vr−Vt)
Since the voltage Vt has a constant value that is determined by electric characteristics of a cell, the wall voltage can be set to any target value by setting the final value Vr of the ramp voltage. In other words, even if there is a minute difference in the voltage Vt between cells, the difference between the voltage Vt and the voltage Vw can be equalized in all cells.
In the initialization for generating microdischarge, a first ramp voltage is applied so as to form appropriate quantity of wall charge between the display electrodes. After that, a second ramp voltage is applied so as to make the wall voltage between the display electrodes close to the target value.
FIG. 24 is a schematic diagram of the conventional driving circuit. In the conventional method, as means for applying a ramp voltage, there is used constant-current circuits 911 and 921 each of which combines a field-effect transistor (FET) and a resistor. In the constant-current circuit 911 for applying a ramp voltage of the positive polarity, the drain of the FET is connected to an electrode of a cell, and the source of the FET is connected to a power source of a potential +V via a resistor. The gate of the FET is supplied with an on/off control signal S10 via a driver 912. The driver 912 includes an isolator 913 such as a photocoupler and converts the on/off control signal S10 into a signal with respect to the power source potential +V. When the gate of the FET is biased so that the FET is turned on, a current flows from the power source to the cell. The resistor restricts the current, and a constant current IC is supplied to the cell. Since the cell is a capacitive load CL to the power source when discharge is not generated, the supply of the constant current increases the voltage applied to the cell at a substantially constant rate. When a ground circuit 930 is activated, charge of the load CL is discharged to the ground line, so that the electrode potential becomes the ground potential. The constant-current circuit 921 for applying a ramp voltage of the negative polarity has substantially the same structure as that of the constant-current circuit 911 except the polarity of the FET. The constant-current circuit 921 is supplied with an on/off control signal S20 via a driver 922. The driver 922 includes an isolator 923 and converts the on/off control signal S20 into a signal with respect to the power source potential −V. When the FET is turned on, a current IC flows from the display electrode to the power source, so that the voltage having the negative polarity applied to the cell increases at a substantially constant rate.
As a concrete example, it is supposed that the output voltage of the driver 912 is 10 volts, the threshold level voltage between the gate and the source of the FET is 3 volts and resistance of the resistor is 50 ohms. In this case, the output current IC of the constant-current circuit 911 is (10−3)/50=0.14 amperes. If capacitance of the load CL is 0.14 microfarads, gradient of the ramp waveform is dV/dt=IC/CL=1 volt per microsecond. This means that the ramp voltage increasing from zero volts reaches 200 volts 200 microseconds after the start of the increasing.
FIG. 25 shows a transition of the driving voltage in the conventional method.
Before microdischarge is generated, capacitance of the load is charged by the whole current supplied from the constant-current circuit. When microdischarge starts, a part of the supplied current becomes a discharge current, so that the current for charging the capacitance decreases. Therefore, the rate of increase in the applied voltage, i.e., the gradient of the ramp waveform is not constant but alters in accordance with whether discharge is generated or not.
In the initialization as an addressing preparation of a certain subframe, if all cells were off (not lighted) in the adjacent subframe (hereinafter, referred to as the previous subframe), the cells have little wall charge at the start of the initialization. Therefore, discharge starts when the applied voltage becomes close to the final value +V. Accordingly, the time Tp1 until the applied voltage reaches the final value +V is relatively short. In the case of the above-mentioned concrete example, the time Tp1 is 200 microseconds. On the contrary, if all cells were lighted in the previous subframe, the cells have residual wall charge at the start of the initialization. Therefore, discharge starts when the applied voltage is still low. For this reason, the time Tp2 until the applied voltage reaches the final value +V is relatively long. For example, microdischarge starts when the applied voltage reaches 100 volts. When the gradient of the ramp waveform decreases from 1 volts per microsecond to 0.5 volts per microsecond, the time Tp2 becomes 300 microseconds.
A pulse width (i.e., an application period) of the applied voltage pulse is set in accordance with the time Tp2. Since the gradient of the ramp waveform varies substantially due to discharge in the conventional method, it is difficult to shorten the pulse width, so there is a problem that the initialization requires a long time. It is desirable that the reset period is as short as possible so as to secure a long time that can be assigned to addressing and sustaining.